Publications

Physical unclonable in-memory computing for simultaneous protecting private data and deep learning models

Published in Nature Communications, 2025

This paper is about physical unclonable in-memory computing, a novel technique for compute-in-memory to achieve robust and effcient edge acceleration.

Recommended citation: Yue, W., Wu, K., Li, Z., Zhou, J., Wang, Z., Zhang, T., ... & Yang, Y. (2025). Physical unclonable in-memory computing for simultaneous protecting private data and deep learning models. Nature Communications, 16(1), 1031.
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A scalable universal Ising machine based on interaction-centric storage and compute-in-memory

Published in Nature Electronics, 2024

This paper is about achieving universal and scalable Ising machine.

Recommended citation: Yue, W., Zhang, T., Jing, Z., Wu, K., Yang, Y., Yang, Z., ... & Yang, Y. (2024). A scalable universal Ising machine based on interaction-centric storage and compute-in-memory. Nature Electronics, 7(10), 904-913.
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Fully Hardware Memristive Neuromorphic Computing Enabled by the Integration of Trainable Dendritic Neurons and High‐Density RRAM Chip

Published in Advanced Functional Materials, 2024

This paper introduces a method of integrating trainable dendritic neurons with RRAM to achieve fully hardware memristive neuromorphic computing.

Recommended citation: Yang, Z., Yue, W., Liu, C., Tao, Y., Tiw, P. J., Yan, L., ... & Yang, Y. (2024). Fully Hardware Memristive Neuromorphic Computing Enabled by the Integration of Trainable Dendritic Neurons and High‐Density RRAM Chip. Advanced Functional Materials, 34(44), 2405618.
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VO2 memristor-based frequency converter with in-situ synthesize and mix for wireless internet-of-things

Published in Nature Communications, 2024

Recommended citation: Liu, C., Tiw, P. J., Zhang, T., Wang, Y., Cai, L., Yuan, R., ... & Yang, Y. (2024). VO2 memristor-based frequency converter with in-situ synthesize and mix for wireless internet-of-things. Nature Communications, 15(1), 1523.
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Probabilistic compute-in-memory design for efficient Markov chain Monte Carlo sampling

Published in IEEE Transactions on Circuits and Systems I: Regular Papers, 2023

Recommended citation: Fu, Y., Shi, D., Fan, A., Yue, W., Yang, Y., Huang, R., & Yan, B. (2023). Probabilistic compute-in-memory design for efficient Markov chain Monte Carlo sampling. IEEE Transactions on Circuits and Systems I: Regular Papers, 71(2), 703-716.
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Integrated memristor network for physiological signal processing

Published in Advanced Electronic Materials, 2023

Recommended citation: Cai, L., Yu, L., Yue, W., Zhu, Y., Yang, Z., Li, Y., ... & Yang, Y. (2023). Integrated memristor network for physiological signal processing. Advanced Electronic Materials, 9(6), 2300021.
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Effect of sea-ice drift on the onset of snowball climate on rapidly rotating aqua-planets

Published in The Astrophysical Journal Letters, 2020

Recommended citation: Yue, W., & Yang, J. (2020). Effect of sea-ice drift on the onset of snowball climate on rapidly rotating aqua-planets. The Astrophysical Journal Letters, 898(1), L19.
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PROCA: Programmable Probabilistic Processing Unit Architecture with Accept/Reject Prediction & Multicore Pipelining for Causal Inference

Published in IEEE International Symposium on High Performance Computer Architecture (HPCA), 2025

Recommended citation: Fu, Y., Fan, A., Yue, W., Zhao, H., Shi, D., Wu, Q., ... & Yan, B. (2025, March). PROCA: Programmable Probabilistic Processing Unit Architecture with Accept/Reject Prediction & Multicore Pipelining for Causal Inference. In 2025 IEEE International Symposium on High Performance Computer Architecture (HPCA) (pp. 761-774). IEEE.
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A 40nm 48.7F2/bit 1T2R Resistive Memory Bitcell Array For Adaptive Vector-Symbolic In-Memory Computing

Published in 2025 IEEE European Solid-State Electronics Research Conference (ESSERC), 1900

Recommended citation: Yue, W., Jing, Z., Ye, L., Xiao, T., ..., Yan, B., and Yang, Y. (2025). A 40nm 48.7F2/bit 1T2R Resistive Memory Bitcell Array For Adaptive Vector-Symbolic In-Memory Computing (accepted). In 2025 European Solid-State Electronics Research Conference (ESSERC), IEEE.
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FPGA-Gym: An FPGA-Accelerated Reinforcement Learning Environment Simulation Framework

Published in NeurIPS 2024 Workshop on Open-World Agents, 2024

Recommended citation: Li, J., Zhao, H., Yue, W., Fu, Y., Shi, D., Fan, A., ... & Yan, B. FPGA-Gym: An FPGA-Accelerated Reinforcement Learning Environment Simulation Framework. In NeurIPS 2024 Workshop on Open-World Agents.
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Multifunctional RRAM Chip with Configurability for Sparsity-Aware in-Memory ISNG Machine

Published in 2024 Conference of Science and Technology for Integrated Circuits (CSTIC), 2024

Recommended citation: Yue, W., Jing, Z., Yan, B., Tao, Y., Zhang, T., Huang, R., & Yang, Y. (2024, March). Multifunctional RRAM Chip with Configurability for Sparsity-Aware in-Memory ISNG Machine. In 2024 Conference of Science and Technology for Integrated Circuits (CSTIC) (pp. 1-3). IEEE.
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A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications

Published in 2022 IEEE International Solid-State Circuits Conference (ISSCC), 2022

Recommended citation: Yan, B., Hsu, J. L., Yu, P. C., Lee, C. C., Zhang, Y., Yue, W., ... & Huang, R. (2022, February). A 1.041-Mb/mm 2 27.38-TOPS/W signed-INT8 dynamic-logic-based ADC-less SRAM compute-in-memory macro in 28nm with reconfigurable bitwise operation for AI and embedded applications. In 2022 IEEE International Solid-State Circuits Conference (ISSCC) (Vol. 65, pp. 188-190). IEEE.
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