A 40nm 48.7F2/bit 1T2R Resistive Memory Bitcell Array For Adaptive Vector-Symbolic In-Memory Computing

Recommended citation: Yue, W., Jing, Z., Ye, L., Xiao, T., ..., Yan, B., and Yang, Y. (2025). A 40nm 48.7F2/bit 1T2R Resistive Memory Bitcell Array For Adaptive Vector-Symbolic In-Memory Computing (accepted). In 2025 European Solid-State Electronics Research Conference (ESSERC), IEEE.
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