Wenshuo Yue

Wenshuo Yue

PhD Candidate at Peking University

Biography

I am a fifth-year Ph.D. student in the Institute for Artificial Intelligence, Peking University, advised by Prof. Yuchao Yang and Prof. Bonan Yan. I received B.S. at Peking University in 2021.

Interests

My research focuses on emerging memory design, novel hardware accelerators, neuromorphic computing, and efficient graph processing. I have 13 published/accepted papers, including 6 as the first or co-first author, in top-tier journals and conferences such as Nature Electronics (IF=33.7) and Nature Communications (IF=14.7). With a strong foundation in both industry and academia, I interned at a startup, where I independently tested and validated the functionality of an SRAM-based in-memory computing chip. During my time at university, I designed, taped out, and successfully tested an RRAM-based in-memory computing chip from scratch, demonstrating my ability to independently lead complex hardware projects.

Publications

First-author papers

  1. Yue, W.#, Zhang, T.#, Jing, Z., Wu, K., Yang, Y., Yang, Z., … & Yang, Y. (2024). A scalable universal Ising machine based on interaction-centric storage and compute-in-memory. Nature Electronics, 7(10), 904-913.

  2. Yue, W., Wu, K., Li Z, Zhou, J., Wang, Z., Zhang, T., …Yang, Y. (2025). Physical Unclonable In-Memory Computing for Simultaneous Protecting Private Data and Deep Learning Models. Nature Communications, 16(1), 1031.

  3. Yue, W., Jing, Z., Ye, L., Xiao, T., …, Yan, B., and Yang, Y. (2025). A 40nm 48.7F2/bit 1T2R Resistive Memory Bitcell Array For Adaptive Vector-Symbolic In-Memory Computing (accepted). In 2025 European Solid-State Electronics Research Conference (ESSERC), IEEE.

  4. Yang, Z.#, Yue, W.#, Liu, C., Tao, Y., Tiw, P. J., Yan, L., … & Yang, Y. (2024). Fully Hardware Memristive Neuromorphic Computing Enabled by the Integration of Trainable Dendritic Neurons and High‐Density RRAM Chip. Advanced Functional Materials, 2405618.

  5. Yue, W., Jing, Z., Yan, B., Tao, Y., Zhang, T., Huang, R., & Yang, Y. (2024, March). Multifunctional RRAM Chip with Configurability for Sparsity-Aware in-Memory ISNG Machine. In 2024 Conference of Science and Technology for Integrated Circuits (CSTIC) (pp. 1-3). IEEE.

  6. Yue, W., & Yang, J. (2020). Effect of sea-ice drift on the onset of snowball climate on rapidly rotating aqua-planets. The Astrophysical Journal Letters, 898(1), L19.

Co-author papers

  1. Yan, B., Hsu, J. L., Yu, P. C., Lee, C. C., Zhang, Y., Yue, W., … & Huang, R. (2022, February). A 1.041-mb/mm 2 27.38-tops/w signed-int8 dynamic-logic-based adc-less sram compute-in-memory macro in 28nm with reconfigurable bitwise operation for ai and embedded applications. In 2022 IEEE International Solid-State Circuits Conference (ISSCC) (Vol. 65, pp. 188-190). IEEE.

  2. Liu, C., Tiw, P. J., Zhang, T., Wang, Y., Cai, L., Yuan, R., Pan, Z., Yue, W., … & Yang, Y. (2024). VO2 memristor-based frequency converter with in-situ synthesize and mix for wireless internet-of-things. Nature Communications, 15(1), 1523.

  3. Fu, Y., Shi, D., Fan, A., Yue, W., Yang, Y., Huang, R., & Yan, B. (2023). Probabilistic Compute-in-Memory Design for Efficient Markov Chain Monte Carlo Sampling. IEEE Transactions on Circuits and Systems I: Regular Papers.

  4. Cai, L., Yu, L., Yue, W., Zhu, Y., Yang, Z., Li, Y., … & Yang, Y. (2023). Integrated memristor network for physiological signal processing. Advanced Electronic Materials, 9(6), 2300021.

  5. Li, J., Zhao, H., Yue, W., Fu, Y., Shi, D., Fan, A., … & Yan, B. (2024). FPGA-Gym: An FPGA-Accelerated Reinforcement Learning Environment Simulation Framework. In NeurIPS 2024 Workshop on Open-World Agents.

  6. Li, J., Zhao, H., Yue, W., Fu, Y., Shi, D., Fan, A., Yang, Y., & Yan, B. (2025). “PEARL: FPGA-Based Reinforcement Learning Acceleration with Pipelined Parallel Environments.” 2025 Design, Automation & Test in Europe Conference & Exhibition (DATE).

  7. Fu, Y., Fan, A., Yue, W., Zhao, H., Shi, D., Wu, Q., Li, J., Zhang, X., Tao, Y., Yang, Y., & Yan, B. (2025). “PROCA: Programmable Probabilistic Processing Unit Architecture with Accept/Reject Prediction & Multicore Pipelining for Causal Inference.” IEEE International Symposium on High-Performance Computer Architecture (HPCA) (pp. 761-774).

Services

Official Reviewer of DAC and AICAS.